1. Field of the Invention
The present invention is directed to a method for simulating a fault in a logic circuit comprising field effect transistors, whereby output bit patterns are derived from the sequence of input bit patterns applied in respectively successive clock periods via a simulation model simulating a fault. Such therefor, output bit patterns are compared to reference patterns valid in a fault-free case and is also directed to a simulation model for implementing the method.
2. Description of the Prior Art
With reference to FIG. 1, a logic circuit is illustrated and it is assumed that a fault of the logic circuit is difficult to recognize or simulate. One therefore proceeds from a digital circuit which contains a portion 1 at the input side and a portion 2 at the output side. The portion 1 comprises a series of digital inputs El . . . En and the portion 2 comprises a series of digital outputs Al . . . An. A logic circuit, for example an inverter 3, to be tested in view of its operability is connected to an output 4 of the portion 1 via its input and connected to an input 5 of the portion 2 of the digital circuit via its output. In the initial condition of this circuit, it is assumed that a bit pattern 1, 1, 0, 1 is applied to the inputs E1, E2, E3 and E4, whereby a logic "1" occurs at the output 4 of an AND gate 6 and, therefore, at the input of the inverter 3. The output of the inverter 3, accordingly, lies at the logic level "0", just as does the first input of an NOR gate 7 which is arranged in the circuit portion 2 of the digital circuit. The second input of the NOR gate 7 is connected to a "0" level via the input 3, so that a "1" is applied to the first input of the AND gate 8 via the output of the NOR gate 7, the second input of the AND gate 8 being applied with a "1" level via the input 4. Accordingly, a "1" level is output to the output Af via the output of the AND gate 8. When, subsequently, a second input pattern 1, 0, 0, 1 is applied at the inputs E1--E4, then the respective logical signals "0", "1", "0" and "0" occur at the output points 4, 5 and at the output of the NOR gate 7 and at the digital output Af as likewise indicated in the drawing.
It is essential, however, that the bit pattern at the input side be applied to the inputs El . . . En in synchronization with a clock signal at the respective beginning of individual, successive clock periods. Likewise, the output patterns derived from these via the portions 1, 3 and 2 are interrogated or, respectively, evaluated at the outputs Al . . . An at the respective beginning of the next-successive sampling periods. The inverter can then comprise a fault so that one of its circuit branches exhibits an inadmissibly low conductivity. Given a circuit constructed in accordance with the integrated circuit technology, for example, the cause of this fault can be excessively-high impedance contacting, a constriction of an interconnect or a threshold voltage shift of a field effect transistor. Given the assumption that this fault is present in the circuit branch (pull-up path) connecting the inverter output to a terminal of the supply voltage, the following effects derive for the occurring output bit pattern. At the beginning of a defined, first clock period, the circuit placed in an initial condition by supplying the input pattern 1, 0, 0, 1 at the inputs E1 . . . E4. A logical "0" is therefore applied to the inverter input. The output of a fault-free inverter would then be reloaded from "0" to "1" within the clock period. Due to the fault, however, the reloading of the inverter output occurs so slowly that the circuit portion 7, 8 and Af connected to the inverter output still evaluates its potential as "0" at the time of evaluation, i.e. at the beginning of the following, second clock period. The signal deviations which are respectively indicated following the oblique strokes at the appertaining circuit portions in FIG. 1 thereby occur. The signal error can be recognized at the digital circuit output Af because a "1" logic level appears instead of the anticipated "0" logic level. Insofar as the inverter input is again occupied with a "0" logic level in the aforementioned second clock period, the delayed reloading operation can be concluded in the clock period. This means that the inverter output is switched to a "1" level delayed by one clock period. The erroneously-delayed signal change at the inverter output can therefore only be recognized at the digital circuit output Af during the first clock period.
A local delay error occurs in a general logic circuit to be tested for operability which, for example, is arranged between a plurality of outputs of a portion 1 and a plurality of inputs of a portion 2 of the digital circuit of FIG. 1 and then two input bit patterns must be successively supplied for the purpose of fault recognition. Of these, the first bit pattern applied in a first clock period is referred to as an initialization pattern and the second pattern applied in the successive clock period is referred to as a fault-recognition pattern. For the above-specified example of a faulty inverter, a possible initialization pattern comprises the bits, 1, 1, 0, 1 for the inputs E1--E4, whereas a fault-recognition pattern is applied to the inputs with the bits 1, 0, 0, 1. The local delay fault can likewise only be recognized in a single clock period when testing a general logic circuit.
In a simulation method, one then proceeds such that the logic circuit to be tested is simulated by a simulation model which is inserted between the circuit portions 1 and 2 of the digital circuit in accordance with the real logic circuit. A defined, local delay error is contained in this simulation model. In a plurality of successive clock periods, a sequence of n-placed bit patterns is then applied to the inputs El . . . En. The respective output patterns derived via the circuit portion 1, the simulation model and the circuit portion 2 then appear at the outputs Al . . . An, these being registered and compared to reference patterns which are determinant for a fault-free case. Each input bit pattern which leads to an output pattern that deviates from the corresponding reference pattern in terms of at least one bit is qualified as a fault-recognition pattern. When a fault-recognition pattern identified in this manner is supplied to the digital circuit to be tested and wherein the simulation model is replaced by a corresponding, realized target logic circuit, then one can conclude the presence of the simulated delay error in the target logic circuit when an output pattern appears at the outputs Al . . . An which corresponds to the pattern that appeared in the simulation method as a consequence of the simulated fault.